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? 2015-2016 microchip technology inc. ds20005434b-page 1 mcp6v91/1u/2/4 features ? high dc precision: -v os drift: 17 nv/c (maximum, v dd =5.5v) -v os : 9 v (maximum) -a ol : 126 db (minimum, v dd =5.5v) - psrr: 117 db (minimum, v dd =5.5v) - cmrr: 118 db (minimum, v dd =5.5v) -e ni : 0.24 v p-p (typical), f = 0.1 hz to 10 hz -e ni : 0.08 v p-p (typical), f = 0.01 hz to 1 hz ? enhanced emi protection: - electromagnetic interference rejection ratio (emirr) at 1.8 ghz: 93 db ? low power and supply voltages: -i q : 1.1 ma/amplifier (typical) - wide supply voltage range: 2.4v to 5.5v ? small packages: - singles in sc70, sot-23 - duals in msop-8, 2x3 tdfn - quads in tssop-14 ?easy to use: - rail-to-rail input/output - gain bandwidth product: 10 mhz (typical) - unity gain stable ? extended temperature range: -40c to +125c typical applications ? portable instrumentation ? sensor conditioning ? temperature measurement ? dc offset correction ? medical instrumentation design aids ? spice macro models ?filterlab ? software ? microchip advanced part selector (maps) ? analog demonstration and evaluation boards ? application notes related parts ? mcp6v11/1u/2/4: zero-drift, low power ? mcp6v31/1u/2/4: zero-drift, low power ? mcp6v61/1u/2/4: zero-drift, 1 mhz ? mcp6v71/1u/2/4: zero-drift, 2 mhz ? mcp6v81/1u/2/4: zero-drift, 5 mhz general description the microchip technology incorporated mcp6v91/1u/2/4 family of operational amplifiers provides input offset voltage correction for very low offset and offset drift. these devices have a gain bandwidth product of 10 mhz (typical). they are unity-gain stable, have virtually no 1/f noise and have good power supply rejection ratio (psrr) and common mode rejection ratio (cmrr). these products operate with a single supply voltage as low as 2.4v, while drawing 1.1 ma/amplifier (typical) of quiescent current. the mcp6v91/1u/2/4 family has enhanced emi protection to minimize any electromagnetic interference from external sources. this feature makes it well suited for emi-sensitive applications such as power lines, radio stations and mobile communications, etc. the mcp6v91/1u/2/4 op amps are offered in single (mcp6v91 and mcp6v91u), dual (mcp6v92) and quad (mcp6v94) packages. they were designed using an advanced cmos process. package types v in + v ss v in ? 1 2 3 5 4 v dd v out mcp6v91 sot-23 mcp6v91u sc70, sot-23 v in ? v ss v out 1 2 3 5 4 v dd v in + v ina + v ina ? v ss 1 2 3 4 8 7 6 5 v outa v dd v outb v inb - v inb + mcp6v92 msop mcp6v92 23 tdfn* v ina + v ina - v ss v outb v inb - 1 2 3 4 8 7 6 5 v inb + v dd v outa ep 9 v ina + v ina - v dd 1 2 3 4 14 13 12 11 v outa v outd v ind - v ind + v ss mcp6v94 tssop v inb - v inb + v outb 5 6 7 10 9 8 v inc + v inc - v outc * includes exposed thermal pad (ep); see tab l e 3 - 1 . 10 mhz, zero-drift op amps
mcp6v91/1u/2/4 ds20005434b-page 2 ? 2015-2016 microchip technology inc. typical application circuit figures 1 and 2 show input offset voltage of the single- channel device mcp6v91 versus ambient temperature for different power supply voltages. figure 1: input offset voltage vs. ambient temperature with v dd =2.4v. figure 2: input offset voltage vs. ambient temperature with v dd =5.5v. as seen in figures 1 and 2 , the mcp6v91/1u op amps have excellent performance across temperature. the input offset voltage temperature drift (tc 1 ) shown is well within the specified maximum values of 17 nv/c at v dd = 5.5v and 24 nv/c at v dd =2.4v. this performance supports applications with stringent dc precision requirements. in many cases, it will not be necessary to correct for temperature effects (i.e., calibrate) in a design. in the other cases, the correction will be small. u 1 mcp6xxx offset voltage correction for power driver c 2 r 2 r 1 r 3 v dd /2 r 4 v in v out r 2 v dd /2 r 5 u 2 mcp6v91 - + - + -8 -6 -4 -2 0 2 4 6 8 -50-25 0 255075100125 input offset voltage (v) ambient temperature (c) 26 samples v dd = 2.4v -8 -6 -4 -2 0 2 4 6 8 -50-25 0 255075100125 input offset voltage (v) ambient temperature (c) 26 samples v dd = 5.5v
? 2015-2016 microchip technology inc. ds20005434b-page 3 mcp6v91/1u/2/4 1.0 electrical characteristics 1.1 absolute maximum ratings ? v dd ?v ss .............................................................................................................................. ...................................6.5v current at input pins ......................................................................................................... .....................................2 ma analog inputs (v in + and v in ?) ( 1 ) ...............................................................................................v ss ? 1.0v to v dd +1.0v all other inputs and outputs .................................................................................................. ..v ss ? 0.3v to v dd +0.3v difference input voltage ...................................................................................................... ...........................|v dd ?v ss | output short circuit current .................................................................................................. ......................... continuous current at output and supply pins ............................................................................................. ......................... 30 ma storage temperature ........................................................................................................... ..................-65c to +150c maximum junction temperature .................................................................................................. ........................ +150c esd protection on all pins (hbm, cdm, mm) mcp6v91/1u ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????? ???????????????????? ? 4kv,1.5kv,400v mcp6v92/4 ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????? ??????????????????????? ? 4kv,1.5kv,300v note 1: see section 4.2.1 ?rail-to-rail inputs? . 1.2 specifications ?notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: dc electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.4v to +5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l = 30 pf (refer to figures 1-4 and 1-5 ). parameters sym. min. typ. max. units conditions input offset input offset voltage v os -9 ? +9 v t a =+25c input offset voltage drift with temperature (linear temperature coefficient) mcp6v91/1u tc 1 -24 ? +24 nv/c t a = -40 to +125c, v dd =2.4v ( note 1 ) tc 1 -17 ? +17 nv/c t a = -40 to +125c, v dd =5.5v ( note 1 ) input offset voltage drift with temperature (linear temperature coefficient) mcp6v92/4 tc 1 -30 ? +30 nv/c t a = -40 to +125c, ( note 1 ) input offset voltage quadratic temperature coefficient mcp6v91/1u tc 2 ?30?pv/c 2 t a = -40 to +125c v dd =2.4v tc 2 ?12?pv/c 2 t a = -40 to +125c v dd =5.5v input offset voltage quadratic temperature coefficient mcp6v92/4 tc 2 ?74?pv/c 2 t a = -40 to +125c v dd =2.4v tc 2 ?48?pv/c 2 t a = -40 to +125c v dd =5.5v note 1: for design guidance only; not tested. 2: figure 2-19 shows how v cml and v cmh changed across temperature for the first production lot.
mcp6v91/1u/2/4 ds20005434b-page 4 ? 2015-2016 microchip technology inc. input offset voltage aging ? v os ? 0.75 ? v 408 hours life test at +150, measured at +25c. power supply rejection ratio psrr 117 137 ? db input bias current and impedance input bias current i b -50 2 +50 pa input bias current across temperature i b ?+10?pat a =+85c i b 0+0.2+1nat a = +125c input offset current i os -400 100 +400 pa input offset current across temperature i os ?75?pat a =+85c i os -500 100 +500 pa t a = +125c common-mode input impedance z cm ?10 13 ||14 ? ? ||pf differential input impedance z diff ?10 13 ||3 ? ? ||pf common mode common-mode input voltage range low v cml ??v ss ?0.2 v note 2 common-mode input voltage range high v cmh v dd +0.3 ? ? v note 2 common-mode rejection ratio cmrr 112 132 ? db v dd =2.4v, v cm = -0.2v to 2.7v ( note 2 ) cmrr 118 140 ? db v dd =5.5v, v cm = -0.2v to 5.8v ( note 2 ) open-loop gain dc open-loop gain (large signal) a ol 119 142 ? db v dd =2.4v, v out = 0.3v to 2.0v a ol 126 158 ? db v dd =5.5v, v out = 0.3v to 5.3v output minimum output voltage swing v ol v ss v ss +35 v ss +120 mv r l =1k ? , g = +2, 0.5v input overdrive v ol ?v ss +7 ? mv r l =10k ? , g = +2, 0.5v input overdrive maximum output voltage swing v oh v dd ?120 v dd ?45 v dd mv r l =1k ? , g = +2, 0.5v input overdrive v oh ?v dd ?9 ? mv r l =10k ? , g = +2, 0.5v input overdrive output short-circuit current i sc ?15?mav dd =2.4v i sc ?40?mav dd =5.5v power supply supply voltage v dd 2.4 ? 5.5 v quiescent current per amplifier i q 0.6 1.1 1.6 ma i o =0 power-on reset (por) trip voltage v por 1.4 1.85 2.2 v table 1-1: dc electrical specifications (continued) electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.4v to +5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l = 30 pf (refer to figures 1-4 and 1-5 ). parameters sym. min. typ. max. units conditions note 1: for design guidance only; not tested. 2: figure 2-19 shows how v cml and v cmh changed across temperature for the first production lot.
? 2015-2016 microchip technology inc. ds20005434b-page 5 mcp6v91/1u/2/4 table 1-2: ac electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.4v to +5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l = 30 pf (refer to figures 1-4 and 1-5 ). parameters sym. min. typ. max. units conditions amplifier ac response gain bandwidth product gbwp ? 10 ? mhz slew rate sr ? 9.5 ? v/s phase margin pm ? 60 ? c g = +1 amplifier noise response input noise voltage e ni ?0.08?v p-p f=0.01hz to 1hz e ni ?0.24?v p-p f = 0.1 hz to 10 hz input noise voltage density e ni ?11?nv/ hz f < 2 khz, v dd =5.5v input noise current density i ni ?6?fa/ hz amplifier distortion ( 1 ) intermodulation distortion (ac) imd ? 35 ? v pk v cm tone = 100 mv pk at 1 khz, g n =11, rti amplifier step response start-up time t str ? 100 ? s g = +1, 0.1% v out settling ( note 2 ) offset correction settling time t stl ?60? sg=+1, v in step of 2v, v os within 100 v of its final value output overdrive recovery time t odr ? 65 ? s g = -10, 0.5v input overdrive to v dd /2, v in 50% point to v out 90% point ( note 3 ) emi protection emi rejection ratio emirr ? 88 ? db v in =0.1v pk , f = 400 mhz ?95? v in =0.1v pk , f = 900 mhz ?93? v in =0.1v pk , f = 1800 mhz ?90? v in =0.1v pk , f = 2400 mhz note 1: these parameters were characterized using the circuit in figure 1-6 . in figures 2-40 and 2-41 , there is an imd tone at dc, a residual tone at 1 khz and other imd tones and clock tones. imd is referred to input (rti). 2: high gains behave differently; see section 4.3.3 ?offset at power-up? . 3: t stl and t odr include some uncertainty due to clock edge timing. table 1-3: temperature specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v dd = +2.4v to +5.5v, v ss =gnd. parameters sym. min. typ. max. units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c note 1 storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5ld-sc70 ? ja ?209 ? c/w thermal resistance, 5ld-sot-23 ? ja ?201 ? c/w thermal resistance, 8l-2x3 tdfn ? ja ?53 ? c/w thermal resistance, 8l-msop ? ja ?211 ? c/w thermal resistance, 14l-tssop ? ja ?100 ? c/w note 1: operation must not cause t j to exceed maximum junction temperature specification (+150c).
mcp6v91/1u/2/4 ds20005434b-page 6 ? 2015-2016 microchip technology inc. 1.3 timing diagrams figure 1-1: amplifier start-up. figure 1-2: offset correction settling time. figure 1-3: output overdrive recovery. 1.4 test circuits the circuits used for most dc and ac tests are shown in figures 1-4 and 1-5 . lay the bypass capacitors out as discussed in section 4.3.10 ?supply bypassing and filtering? . r n is equal to the parallel combination of r f and r g to minimize bias current effects. figure 1-4: ac and dc test circuit for most noninverting gain conditions. figure 1-5: ac and dc test circuit for most inverting gain conditions. the circuit in figure 1-6 tests the input?s dynamic behavior (i.e., imd, t str , t stl and t odr ). the potentiometer balances the resistor network (v out should equal v ref at dc). the op amp?s common-mode input voltage is v cm =v in /2. the error at the input (v err ) appears at v out with a noise gain of 10 v/v. figure 1-6: test circuit for dynamic input behavior. v dd v out 1.001(v dd /3) 0.999(v dd /3) t str 0v 2.4v to 5.5v 2.4v v in v os v os +100v v os ?100v t stl v in v out v dd v ss t odr t odr v dd /2 v dd r g r f r n v out v in v dd /3 1f c l r l v l 100 nf r iso mcp6v9x + - v dd r g r f r n v out v dd /3 v in 1f c l r l v l 100 nf r iso mcp6v9x + - v dd v out 1f c l v l r iso 11.0 k ? 249 ? 11.0 k ? 500 ? v in v ref =v dd /3 0.1% 0.1% 25 turn 100 k ? 100 k ? 0.1% 0.1% r l 0 ? 30 pf open 100 nf 1% mcp6v9x
? 2015-2016 microchip technology inc. ds20005434b-page 7 mcp6v91/1u/2/4 2.0 typical performance curves note: unless otherwise indicated, t a =+25c, v dd = +2.4v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l =30pf. 2.1 dc input precision figure 2-1: input offset voltage. figure 2-2: input offset voltage drift. figure 2-3: input offset voltage quadratic temperature coefficient. figure 2-4: input offset voltage vs. power supply voltage with v cm =v cml . figure 2-5: input offset voltage vs. power supply voltage with v cm =v cmh . figure 2-6: input offset voltage vs. output voltage with v dd =2.4v. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 5% 10% 15% 20% 25% 30% -5 -4 -3 -2 -1 0 1 2 3 4 5 percentage of occurrences input offset voltage (v) 26 samples t a = +25c v dd = 2.4v v dd = 5.5v mcp6v91 0% 5% 10% 15% 20% 25% 30% -10-8-6-4-20246810 percentage of occurrences input offset voltage drift; tc 1 (nv/c) 26 samples t a = -40c to +125c v dd = 2.4v v dd = 5.5v mcp6v91 0% 5% 10% 15% 20% 25% 30% 35% -100 -80 -60 -40 -20 0 20 40 60 80 100 percentage of occurrences input offset voltage's quadratic temp co; tc 2 (pv/c 2 ) 26 samples t a = -40c to +125c v dd = 5.5v v dd = 2.4v mcp6v91 -8 -6 -4 -2 0 2 4 6 8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 input offset voltage (v) power supply voltage (v) representative part v cm = 0.1v t a = -40c t a = +25c t a = +85c t a = +125c -8 -6 -4 -2 0 2 4 6 8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 input offset voltage (v) power supply voltage (v) representative part v cm = v dd ?0.1v t a = -40c t a = +25c t a = +85c t a = +125c -8 -6 -4 -2 0 2 4 6 8 0.00.20.40.60.81.01.21.41.61.82.02.22.4 input offset voltage (v) output voltage (v) representative part v dd = 2.4v t a = -40c t a = +25c t a = +85c t a = +125c
mcp6v91/1u/2/4 ds20005434b-page 8 ? 2015-2016 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.4v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l =30pf. figure 2-7: input offset voltage vs. output voltage with v dd =5.5v. figure 2-8: input offset voltage vs. common-mode voltage with v dd =2.4v. figure 2-9: input offset voltage vs. common-mode voltage with v dd =5.5v. figure 2-10: common-mode rejection ratio. figure 2-11: power supply rejection ratio. figure 2-12: dc open-loop gain. -8 -6 -4 -2 0 2 4 6 8 0.0 0.5 1.0 1.5 2.0 2.5 3 .0 3.5 4.0 4.5 5.0 5.5 input offset voltage (v) output voltage (v) representative part v dd = 5.5v t a = -40c t a = +25c t a = +85c t a = +125c -8 -6 -4 -2 0 2 4 6 8 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 input offset voltage (v) common mode input voltage (v) representative part v dd = 2.4v t a = -40c t a = +25c t a = +85c t a = +125c -8 -6 -4 -2 0 2 4 6 8 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input offset voltage (v) common mode input voltage (v) representative part v dd = 5.5v t a = -40c t a = +25c t a = +85c t a = +125c 0% 10% 20% 30% 40% 50% 60% -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 percentage of occurrences 1/cmrr (v/v) tester data 599 samples t a = +25oc v dd = 2.4v v dd = 5.5v 0% 10% 20% 30% 40% 50% 60% -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 percentage of occurrences 1/psrr (v/v) tester data 599 samples t a = +25oc 0% 10% 20% 30% 40% 50% 60% 70% 80% -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 percentage of occurrences 1/a ol (v/v) tester data 599 samples t a = +25oc v dd = 5.5v v dd = 2.4v
? 2015-2016 microchip technology inc. ds20005434b-page 9 mcp6v91/1u/2/4 note: unless otherwise indicated, t a =+25c, v dd = +2.4v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l =30pf. figure 2-13: cmrr and psrr vs. ambient temperature. figure 2-14: dc open-loop gain vs. ambient temperature. figure 2-15: input bias and offset currents vs. common-mode input voltage with t a = +85c. figure 2-16: input bias and offset currents vs. common-mode input voltage with t a = +125c. figure 2-17: input bias and offset currents vs. ambient temperature with v dd =5.5v. figure 2-18: input bias current vs. input voltage (below v ss ). 100 105 110 115 120 125 130 135 140 145 150 155 160 -50 -25 0 25 50 75 100 125 cmrr, psrr (db) ambient temperature (c) cmrr at v dd = 5.5v cmrr at v dd = 2.4v psrr typical gains 100 105 110 115 120 125 130 135 140 145 150 155 160 -50 -25 0 25 50 75 100 125 dc open-loop gain (db) ambient temperature (c) v dd = 2.4v v dd = 5.5v typical gains -500 -400 -300 -200 -100 0 100 200 300 400 500 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input bias and offset currents (pa) input common mode voltage (v) in p ut bias current input offset current v dd = 5.5 v t a = +85 oc -500 -400 -300 -200 -100 0 100 200 300 400 500 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input bias and offset currents (pa) input common mode voltage (v) in p ut bias current input offset current v dd = 5.5 v t a = +125 oc 25 35 45 55 65 75 85 95 105 115 125 input bias, offset currents (a) ambient temperature (c) in p ut bias current input offset current v dd = 5.5 v 1n 100 p 10 p 1 p 0.1 p -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input current magnitude (a) input voltage (v) t a = +125c t a = +85c t a = +25c t a = - 40c 1m 10 100n 10n 1n 100 1 100p 10p
mcp6v91/1u/2/4 ds20005434b-page 10 ? 2015-2016 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.4v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l =30pf. 2.2 other dc voltages and currents figure 2-19: input common-mode voltage headroom (range) vs. ambient temperature. figure 2-20: output voltage headroom vs. output current. figure 2-21: output voltage headroom vs. ambient temperature. figure 2-22: output short-circuit current vs. power supply voltage. figure 2-23: supply current vs. power supply voltage. figure 2-24: power-on reset trip voltage. -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 common-mode input voltage headroom (v) ambient temperature (c) v dd = 2.4v v dd = 5.5v lower (v cml ?v ss ) upper (v cmh ?v dd ) 1 wafer lot 1 10 100 1000 0.1 1 10 output voltage headroom (mv) output cu rrent magnitude (ma) v dd = 5.5v v dd = 2.4v v dd -v oh v ol -v ss 0 10 20 30 40 50 60 70 80 -50-25 0 255075100125 output voltage headroom (mv) ambient temperature (c) v dd -v oh v dd = 5.5v v ol -v ss v dd = 2.4v r l = 1 k -80 -60 -40 -20 0 20 40 60 80 0.511.522.533.544.555.56 output short circuit current (ma) power supply voltage (v) t a = +125c t a = +85c t a = +25c t a = -40c t a = +125c t a = +85c t a = +25c t a = -40c 0 200 400 600 800 1000 1200 1400 1600 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 quiescent current (a/amplifier) power supply voltage (v) t a = +125c t a = +85c t a = +25c t a = -40c 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 percentage of occurrences por trip voltage (v) 430 samples 1 wafer lot t a = +25oc
? 2015-2016 microchip technology inc. ds20005434b-page 11 mcp6v91/1u/2/4 note: unless otherwise indicated, t a =+25c, v dd = +2.4v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l =30pf. figure 2-25: power-on reset voltage vs. ambient temperature. 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 -50-25 0 255075100125 por trip voltage (v) ambient temperature (c)
mcp6v91/1u/2/4 ds20005434b-page 12 ? 2015-2016 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.4v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l =30pf. 2.3 frequency response figure 2-26: cmrr and psrr vs. frequency. figure 2-27: open-loop gain vs. frequency with v dd =2.4v. figure 2-28: open-loop gain vs. frequency with v dd =5.5v. figure 2-29: gain bandwidth product and phase margin vs. ambient temperature. figure 2-30: gain bandwidth product and phase margin vs. common-mode input voltage. figure 2-31: gain bandwidth product and phase margin vs. output voltage. 0 20 40 60 80 100 120 140 cmrr, psrr (db) frequency (hz) 100 1k 10k 100k 1m 10m cmrr psrr+ psrr- representative part -270 -240 -210 -180 -150 -120 -90 -60 -30 -20 -10 0 10 20 30 40 50 60 1.e+04 1.e+05 1.e+06 1.e+07 f (hz) open-loop phase () open-loop gain (db) open-loop gain open-loop phase v dd = 2.4v c l = 30 pf 10k 100k 1m 10m -270 -240 -210 -180 -150 -120 -90 -60 -30 -20 -10 0 10 20 30 40 50 60 1.e+04 1.e+05 1.e+06 1.e+07 f (hz) open-loop phase () open-loop gain (db) open-loop gain open-loop phase v dd = 5.5v c l = 30 pf 10k 100k 1m 10m 10 20 30 40 50 60 70 80 6 7 8 9 10 11 12 13 -50 -25 0 25 50 75 100 125 gain bandwidth product (mhz) ambient temperature (c) gbwp pm v dd = 2.4v phase margin () v dd = 5.5v 30 40 50 60 70 80 90 0 2 4 6 8 10 12 -10123456 phase margin (o) gain bandwidth product (mhz) common mode input voltage (v) v dd = 5.5v v dd = 2.4v pm gbwp 30 40 50 60 70 80 90 2 4 6 8 10 12 14 0123456 phase margin (o) gain bandwidth product (mhz) output voltage (v) v dd = 5.5v gbwp pm v dd = 2.4v
? 2015-2016 microchip technology inc. ds20005434b-page 13 mcp6v91/1u/2/4 note: unless otherwise indicated, t a =+25c, v dd = +2.4v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l =30pf. figure 2-32: closed-loop output impedance vs. frequency with v dd =2.2v. figure 2-33: closed-loop output impedance vs. frequency with v dd =5.5v. figure 2-34: maximum output voltage swing vs. frequency. figure 2-35: emirr vs. frequency. figure 2-36: emirr vs. input voltage. figure 2-37: channel-to channel separation vs. frequency. 0.1 1 10 100 1000 closed loop output impedance ( ) frequency (hz) g n : 101 v/v 11 v/v 1 v/v 1k 10k 100k 1m 10m v dd = 2.4v 0.1 1 10 100 1000 1.0e+03 1.0e+04 1.0e +05 1.0e+06 1.0e+07 closed loop output impedance ( ) frequency (hz) g n : 101 v/v 11 v/v 1 v/v 1k 10k 100k 1m 10m v dd =5.5v 0.1 1 10 output voltage swing (v p-p ) frequency (hz) v dd = 2.4v v dd = 5.5v 10k 100k 1m 10m 100m 10 20 30 40 50 60 70 80 90 100 110 120 10 100 1000 10000 emirr (db) frequency (hz) 10m 100m 1g 10g v pk = 100 mv v dd = 5.5v 0 20 40 60 80 100 120 0.01 0.10 1.00 10.00 emirr (db) rf input peak voltage (vp) emirr at 2400 mhz emirr at 1800 mhz emirr at 900 mhz emirr at 400 mhz v dd = 5.5v 80 90 100 110 120 130 140 150 1.e+03 1.e+04 1.e+05 1.e+06 channel-to-channel separation rti (db) frequency (hz) 10k 100k 1m v dd = 5.5v v dd = 2.4v 1k
mcp6v91/1u/2/4 ds20005434b-page 14 ? 2015-2016 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.4v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l =30pf. 2.4 input noise and distortion figure 2-38: input noise voltage density and integrated input noise voltage vs. frequency. figure 2-39: input noise voltage density vs. input common-mode voltage. figure 2-40: intermodulation distortion vs. frequency with v cm disturbance (see figure 1-6 ). figure 2-41: intermodulation distortion vs. frequency with v dd disturbance (see figure 1-6 ). figure 2-42: input noise vs. time with 1 hz and 10 hz filters and v dd =2.4v. figure 2-43: input noise vs. time with 1 hz and 10 hz filters and v dd =5.5v. 1 10 100 1000 1 10 100 1000 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 frequency (hz) integrated input noise voltage; e ni (v p-p ) input noise voltage density; e ni (nv/ hz) e ni e ni (0 hz to f) v dd = 5.5v, red v dd = 2.4v, blue 1 10 100 1k 10k 100k 0 5 10 15 20 25 30 -0.500.511.522.533.544.555.56 input noise voltage density (nv/ hz) common mode input voltage (v) v dd = 2.4v v dd = 5.5v f < 2 khz 1.e-2 1.e-1 1.e+0 1.e+1 1.e+2 1.e+3 1 10 100 1000 10000 100000 imd spectrum, rti (v pk ) frequency (hz) 1 10 100 1k 10k 100k 1m 100 10 1 100n 10n g = 11 v/v v cm tone = 100 mv pk , f = 1 khz dc tone residual 1 khz tone (due to resistor mismatch) ? f = 64 hz ? f = 2 hz v dd = 2.4v v dd = 5.5v 1.e-2 1.e-1 1.e+0 1.e+1 1.e+2 1.e+3 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 imd spectrum, rti (v pk ) frequency (hz) 1 10 100 1k 10k 100k 1m 100 10 1 100n 10n g = 11 v/v v dd tone = 100 mv pk , f = 1 khz dc tone residual 1 khz tone ? f = 64 hz ? f = 2 hz v dd = 2.4v v dd = 5.5v 0 102030405060708090100 input noise voltage; e ni (t) (0.1 v/div) time (s) v dd = 2.4v npbw = 10 hz npbw = 1 hz 0 102030405060708090100 input noise voltage; e ni (t) (0.1 v/div) time (s) v dd = 5.5v npbw = 10 hz npbw = 1 hz
? 2015-2016 microchip technology inc. ds20005434b-page 15 mcp6v91/1u/2/4 note: unless otherwise indicated, t a =+25c, v dd = +2.4v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l =30pf. 2.5 time response figure 2-44: input offset voltage vs. time with temperature change. figure 2-45: input offset voltage vs. time at power-up. figure 2-46: the mcp6v91/1u/2/4 family shows no input phase reversal with overdrive. figure 2-47: noninverting small signal step response. figure 2-48: noninverting large signal step response. figure 2-49: inverting small signal step response. -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 -10 -5 0 5 10 15 20 25 30 35 40 45 pcb temperature (oc) input offset voltage (v) time (s) v dd = 5.5v v dd = 2.4v t pcb v os temperature is increased using a heat gun for 5 seconds 0 10 20 30 40 50 60 70 80 90 100 110 120 -1 0 1 2 3 4 5 6 -5 0 5 10 15 20 25 30 012345678910 power supply voltage (v) input offset voltage (mv) time (ms) v dd = 5.5v g = +1 v/v por trip point v dd v os -1 0 1 2 3 4 5 6 input, output voltages (v) time (1 s/div) v dd = 5.5 v g = +1 v/v v out v in output voltage (20mv/div) time (s) v dd = 5.5v g = +1 v/v v in v out 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 3.5 4 output voltage (v) time (s) v dd = 5.5 v g = +1 v/v v out v in 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 output voltage (20 mv/div) time (s) v dd = 5.5 v g = -1 v/v v in v out
mcp6v91/1u/2/4 ds20005434b-page 16 ? 2015-2016 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.4v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k ? to v l and c l =30pf. figure 2-50: inverting large signal step response. figure 2-51: slew rate vs. ambient temperature. figure 2-52: output overdrive recovery vs. time with g = -10 v/v. figure 2-53: output overdrive recovery time vs. inverting gain. 0 1 2 3 4 5 6 00.511.522.533.54 output voltage (v) time (s) v dd = 5.5 v g = -1 v/v v in v out 5.0 7.0 9.0 11.0 13.0 15.0 -50-25 0 255075100125 slew rate (v/s) ambient temperature (c) falling edge, v dd = 5.5v rising edge, v dd = 2.4v falling edge, v dd = 2.4v rising edge, v dd = 5.5v -1 0 1 2 3 4 5 6 7 output voltage (v) time (50 us/div) v dd = 5.5 v g = -10 v/v 0.5v overdrive v out gv in v out gv in 1 10 100 1000 overdrive recovery time (s) inverting gain magnitude (v/v) 100 10 1 0.5v input overdrive 1m v dd = 2.4v v dd = 5.5v t odr , high t odr , low
? 2015-2016 microchip technology inc. ds20005434b-page 17 mcp6v91/1u/2/4 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . 3.1 analog outputs (v out , v outa , v outb , v outc , v outd ) the analog output pins (v out ) are low-impedance voltage sources. 3.2 analog inputs (v in +, v in -, v inb +, v inb -, v inc -, v inc +, v ind -, v ind +) the noninverting and inverting inputs (v in +, v in ?, ?) are high-impedance cmos inputs with low bias currents. 3.3 power supply pins (v dd , v ss ) the positive power supply (v dd ) is 2.4v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need bypass capacitors. 3.4 exposed thermal pad (ep) there is an internal connection between the exposed thermal pad (ep) and the vss pin; they must be connected to the same potential on the printed circuit board (pcb). this pad can be connected to a pcb ground plane to provide a larger heat sink. this improves the package thermal resistance ( ja ). table 3-1: pin function table mcp6v91 mcp6v91u mcp6v92 mcp6v94 symbol description sot-23 sot-23, sc70 2x3 tdfn msop tssop 1411 1v out output 4322 2v in ? inverting input 3133 3v in + noninverting input 5588 4 v dd positive power supply ?? 5 5 5 v inb + noninverting input (op amp b) ?? 6 6 6 v inb - inverting input (op amp b) ?? 7 7 7 v outb output (op amp b) ???? 8 v outc output (op amp c) ???? 9 v inc - inverting input (op amp c) ???? 10v inc + noninverting input (op amp c) 224411v ss negative power supply ???? 12v ind + noninverting input (op amp d) ???? 13 v ind - inverting input (op amp d) ???? 14v outd output (op amp d) ? ? 9 ? ? ep exposed thermal pad (ep); must be connected to v ss
mcp6v91/1u/2/4 ds20005434b-page 18 ? 2015-2016 microchip technology inc. 4.0 applications the mcp6v91/1u/2/4 family of zero-drift op amps is manufactured using microchip?s state-of-the-art cmos process. it is designed for precision applications with requirements for small packages and low power. its low supply voltage and low quiescent current make the mcp6v91/1u/2/4 devices ideal for battery-powered applications. 4.1 overview of zero-drift operation figure 4-1 shows a simplified diagram of the mcp6v91/1u/2/4 zero-drift op amp. this diagram will be used to explain how slow voltage errors are reduced in this architecture (much better v os , ? v os / ? t a (tc 1 ), cmrr, psrr, a ol and 1/f noise). figure 4-1: simplified zero-drift op amp functional diagram. 4.1.1 building blocks the main amplifier is designed for high gain and bandwidth, with a differential topology. its main input pair (+ and - pins at the top left) is used for the higher frequency portion of the input signal. its auxiliary input pair (+ and - pins at the bottom left) is used for the low-frequency portion of the input signal and corrects the op amp?s input offset voltage. both inputs are added together internally. the auxiliary amplifier, chopper input switches and chopper output switches provide a high dc gain to the input signal. dc errors are modulated to higher frequencies, while white noise is modulated to a low frequency. the low-pass filter reduces high-frequency content, including harmonics of the chopping clock. the output buffer drives external loads at the v out pin (v ref is an internal reference voltage). the oscillator runs at f osc1 = 200 khz. its output is divided by two, to produce the chopping clock rate of f chop = 100 khz. the internal power-on reset (por) starts the part in a known good state, protecting against power supply brown-outs. the digital control block controls switching and por events. 4.1.2 chopping action figure 4-2 shows the amplifier connections for the first phase of the chopping clock and figure 4-3 shows the connections for the second phase. its slow voltage errors alternate in polarity, making the average error small. figure 4-2: first chopping clock phase; equivalent amplifier diagram. figure 4-3: second chopping clock phase; equivalent amplifier diagram. v in + v in ? main buffer v out v ref amp. output nc aux. amp. chopper input switches chopper output switches oscillator low-pass filter por digital control + - + - + - + - + - + - v in + v in ? main amp. nc aux. amp. low-pass filter + - + - + - + - + - v in + v in ? main amp. nc aux. amp. low-pass filter + - + - + - + - + -
? 2015-2016 microchip technology inc. ds20005434b-page 19 mcp6v91/1u/2/4 4.1.3 intermodulation distortion (imd) these op amps will show intermodulation distortion (imd) products when an ac signal is present. the signal and clock can be decomposed into sine wave tones (fourier series components). these tones interact with the zero-drift circuitry?s nonlinear response to produce imd tones at sum and difference frequencies. each of the square wave clock?s harmonics has a series of imd tones centered on it (see figures 2-40 and 2-41 ). 4.2 other functional blocks 4.2.1 rail-to-rail inputs the input stage of the mcp6v91/1u/2/4 op amps uses two differential cmos input stages in parallel. one operates at low common-mode input voltage (v cm , which is approximately equal to v in + and v in - in normal operation), and the other operates at high v cm . with this topology, the input operates with v cm up to v dd + 0.3v and down to v ss ? 0.2v, at +25c (see figure 2-19 ). the input offset voltage (v os ) is measured at v cm =v ss ? 0.2v and v dd +0.3v to ensure proper operation. 4.2.1.1 phase reversal the input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-46 shows an input voltage exceeding both supplies with no phase inversion. 4.2.1.2 input voltage limits in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see section 1.1 ?absolute maximum ratings ?? ). this requirement is independent of the input current limits discussed later on. the esd protection on the inputs can be depicted as shown in figure 4-4 . this structure was chosen to protect the input transistors against many (but not all) overvoltage conditions and to minimize input bias current (i b ). figure 4-4: simplified analog input esd structures. the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages well above v dd ; their breakdown voltage is high enough to allow normal operation but not low enough to protect against slow overvoltage (beyond v dd ) events. very fast esd events (that meet the specification) are limited so that damage does not occur. in some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; figure 4-5 shows one approach to protecting these inputs. d 1 and d 2 may be small signal silicon diodes, schottky diodes for lower clamping voltages or diode-connected fets for low leakage. figure 4-5: protecting the analog inputs against high voltages. bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in ? v 1 v dd d 1 v out v 2 d 2 u 1 mcp6v9x + -
mcp6v91/1u/2/4 ds20005434b-page 20 ? 2015-2016 microchip technology inc. 4.2.1.3 input current limits in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see section 1.1 ?absolute maximum ratings ?? ). this requirement is independent of the voltage limits discussed previously. figure 4-6 shows one approach to protecting these inputs. the r 1 and r 2 resistors limit the possible current in or out of the input pins (and into d 1 and d 2 ). the diode currents will dump onto v dd . figure 4-6: protecting the analog inputs against high currents. it is also possible to connect the diodes to the left of the r 1 and r 2 resistors. in this case, the currents through the d 1 and d 2 diodes need to be limited by some other mechanism. the resistors then serve as in-rush current limiters; the dc current into the input pins (v in + and v in -) should be very small. a significant amount of current can flow out of the inputs (through the esd diodes) when the common- mode input voltage (v cm ) is below ground (v ss ) (see figure 2-18 ). 4.2.2 rail-to-rail output the output voltage range of the mcp6v91/1u/2/4 zero-drift op amps is v dd ? 9 mv (typical) and v ss +7mv (typical) when r l =10k ? is connected to v dd /2 and v dd = 5.5v. refer to figures 2-20 and 2-21 for more information. this op amp is designed to drive light loads; use another amplifier to buffer the output from heavy loads. 4.3 application tips 4.3.1 input offset voltage over temperature table 1-1 gives both the linear and quadratic temperature coefficients (tc 1 and tc 2 ) of input offset voltage. the input offset voltage, at any temperature in the specified range, can be calculated as follows: equation 4-1: 4.3.2 dc gain plots figures 2-10 to 2-12 are histograms of the reciprocals (in units of v/v) of cmrr, psrr and a ol , respectively. they represent the change in input offset voltage (v os ) with a change in common-mode input voltage (v cm ), power supply voltage (v dd ) and output voltage (v out ). the histograms are based on data taken with the production test equipment and the results reflect the trade-off between accuracy and test time. the actual performance of the devices is typically higher than shown in figures 2-10 to 2-12 . the 1/a ol histogram is centered near 0 v/v because the measurements are dominated by the op amp?s input noise. the negative values shown represent noise and tester limitations, not unstable behavior. production tests make multiple v os measurements, which validates an op amp's stability; an unstable part would show greater v os variability or the output would stick at one of the supply rails. 4.3.3 offset at power-up when these parts power up, the input offset (v os ) starts at its uncorrected value (usually less than 5 mv). circuits with high dc gain can cause the output to reach one of the two rails. in this case, the time to a valid output is delayed by an output overdrive time (like t odr ) in addition to the start-up time (like t str ). it can be simple to avoid this extra start-up time. reducing the gain is one method. adding a capacitor across the feedback resistor (r f ) is another method. v 1 r 1 v dd d 1 min(r 1 ,r 2 )> v ss ?min(v 1 ,v 2 ) 2ma v out v 2 r 2 d 2 min(r 1 ,r 2 )> max(v 1 ,v 2 )?v dd 2ma u 1 mcp6v9x + - v os t a ?? v os tc 1 ? ttc 2 ? t 2 ++ = where: ? t=t a ?25c v os (t a ) = input offset voltage at t a v os = input offset voltage at +25c tc 1 = linear temperature coefficient tc 2 = quadratic temperature coefficient
? 2015-2016 microchip technology inc. ds20005434b-page 21 mcp6v91/1u/2/4 4.3.4 source resistances the input bias currents have two significant components: switching glitches that dominate at room temperature and below, and input esd diode leakage currents that dominate at +85c and above. make the resistances seen by the inputs small and equal. this minimizes the output offset caused by the input bias currents. the inputs should see a resistance on the order of 10 ? to 1 k ? at high frequencies (i.e., above 1 mhz). this helps minimize the impact of switching glitches, which are very fast, on overall performance. in some cases, it may be necessary to add resistors in series with the inputs to achieve this improvement in performance. small input resistances may be needed for high gains. without them, parasitic capacitances might cause positive feedback and instability. 4.3.5 source capacitance the capacitances seen by the two inputs should be small. large input capacitances and source resistances, together with high gain, can lead to positive feedback and instability. 4.3.6 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. these zero-drift op amps have a different output impedance than most op amps, due to their unique topology. when driving a capacitive load with these op amps, a series resistor at the output (r iso in figure 4-7 ) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-7: output resistor, r iso , stabilizes capacitive loads. figure 4-8 gives recommended r iso values for different capacitive loads and gains. the x-axis is the load capacitance (c l ). the y-axis is the resistance (r iso ). g n is the circuit?s noise gain. for noninverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -1 v/v gives g n =+2v/v). figure 4-8: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot. modify the r iso value until the response is reasonable. bench evaluation is helpful. 4.3.7 stabilizing output loads this family of zero-drift op amps has an output impedance that has a double zero when the gain is low (see figures 2-32 and 2-33 ). this can cause a large phase shift in feedback networks that have low- impedance near the part?s bandwidth. this large phase shift can cause stability problems. figure 4-9 shows that the load on the output is (r l +r iso )||(r f +r g ), where r iso is before the load (like figure 4-7 ). this load needs to be large enough to maintain stability; it should be at least 10 k ? . figure 4-9: output load. r iso c l v out u 1 mcp6v9x - + 1 10 100 1000 recommended r iso ( ) normalized load capacitance; c l / g n (f) g n : 1 v/v 10 v/v 100 v/v v dd = 5.5 v r l = 10 k 1p 10p 100p 1n 10n 100n 1 r g r f v out u 1 mcp6v9x r l c l - + r iso
mcp6v91/1u/2/4 ds20005434b-page 22 ? 2015-2016 microchip technology inc. 4.3.8 gain peaking figure 4-10 shows an op amp circuit that represents noninverting amplifiers (v m is a dc voltage and v p is the input) or inverting amplifiers (v p is a dc voltage and v m is the input). the c n and c g capacitances represent the total capacitance at the input pins; they include the op amp?s common-mode input capacitance (c cm ), board parasitic capacitance and any capacitor placed in parallel. the c fp capacitance represents the parasitic capacitance coupling the output and noninverting input pins. figure 4-10: amplifier with parasitic capacitance. c g acts in parallel with r g (except for a gain of +1 v/v), which causes an increase in gain at high frequencies. c g also reduces the phase margin of the feedback loop, which becomes less stable. this effect can be reduced by reducing either c g or r f ||r g . c n and r n form a low-pass filter that affects the signal at v p . this filter has a single real pole at 1/(2 r n c n ). the largest value of r f that should be used depends on noise gain (see g n in section 4.3.6 ?capacitive loads? ), c g and the open-loop gain?s phase shift. an approximate limit for r f is: equation 4-2: some applications may modify these values to reduce either output loading or gain peaking (step-response overshoot). at high gains, r n needs to be small in order to prevent positive feedback and oscillations. large c n values can also help. 4.3.9 reducing undesired noise and signals reduce undesired noise and signals with: ? low-bandwidth signal filters: - minimize random analog noise - reduce interfering signals ? good printed circuit board (pcb) layout techniques: - minimize crosstalk - minimize parasitic capacitances and inductances that interact with fast-switching edges ? good power supply design: - isolation from other parts - filtering of interference on supply line(s) 4.3.10 supply bypassing and filtering with this family of operational amplifiers, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm of the pin for good high-frequency performance. these parts also need a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with other low-noise analog parts. in some cases, high-frequency power supply noise (e.g., switched mode power supplies) may cause undue intermodulation distortion with a dc offset shift; this noise needs to be filtered. adding a small resistor into the supply connection can be helpful. 4.3.11 pcb design for dc precision in order to achieve dc precision on the order of 1 v, many physical errors need to be minimized. the design of the pcb, the wiring and the thermal environment have a strong impact on the precision achieved. a poor pcb design can easily be more than 100 times worse than the mcp6v91/1u/2/4 op amps? minimum and maximum specifications. 4.3.11.1 pcb layout any time two dissimilar metals are joined together, a temperature-dependent voltage appears across the junction (the seebeck or thermojunction effect). this effect is used in thermocouples to measure temperature. the following are examples of thermojunctions on a pcb: ? components (resistors, op amps, ?) soldered to a copper pad ? wires mechanically attached to the pcb ? jumpers ? solder joints ?pcb vias r g r f v out u 1 mcp6v9x c g r n c n v m v p c fp + - r f 10 k ? 3.5 pf c g --------------- g n 2 ? ? ?
? 2015-2016 microchip technology inc. ds20005434b-page 23 mcp6v91/1u/2/4 typical thermojunctions have temperature-to-voltage conversion coefficients of 1 to 100 v/c (sometimes higher). microchip?s an1258 ? op amp precision design: pcb layout techniques ? (ds01258) contains in-depth information on pcb layout techniques that minimize thermojunction effects. it also discusses other effects, such as crosstalk, impedances, mechanical stresses and humidity. 4.3.11.2 crosstalk dc crosstalk causes offsets that appear as a larger input offset voltage. common causes include: ? common-mode noise (remote sensors) ? ground loops (current return paths) ? power supply coupling interference from the mains (usually 50 hz or 60 hz) and other ac sources can also affect the dc performance. nonlinear distortion can convert these signals to multiple tones, including a dc shift in voltage. when the signal is sampled by an adc, these ac signals can also be aliased to dc, causing an apparent shift in offset. to reduce interference: - keep traces and wires as short as possible - use shielding - use ground plane (at least a star ground) - place the input signal source near the dut - use good pcb layout techniques - use a separate power supply filter (bypass capacitors) for these zero-drift op amps 4.3.11.3 miscellaneous effects keep the resistances seen by the input pins as small and as near to equal as possible, to minimize bias current-related offsets. make the (trace) capacitances seen by the input pins small and equal. this is helpful in minimizing switching glitch-induced offset voltages. bending a coax cable with a radius that is too small causes a small voltage drop to appear on the center conductor (the triboelectric effect). make sure the bending radius is large enough to keep the conductors and insulation in full contact. mechanical stresses can make some capacitor types (such as some ceramics) output small voltages. use more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration. humidity can cause electrochemical potential voltages to appear in a circuit. proper pcb cleaning helps, as does the use of encapsulants. 4.4 typical applications 4.4.1 wheatstone bridge many sensors are configured as wheatstone bridges. strain gauges and pressure sensors are two common examples. these signals can be small and the common-mode noise large. amplifier designs with high differential gain are desirable. figure 4-11 shows how to interface to a wheatstone bridge with a minimum of components. because the circuit is not symmetric, the adc input is single-ended and there is a minimum of filtering; the cmrr is good enough for moderate common-mode noise. figure 4-11: simple design. 4.4.2 resistance temperature detector (rtd) sensor the ratiometric circuit in figure 4-12 conditions a two-wire rtd for applications with a limited temperature range. u 1 acts as a difference amplifier with a low-frequency pole. the sensor?s wiring resistance (r w ) is corrected in firmware. failure (open) of the rtd is detected by an out-of-range voltage. figure 4-12: rtd sensor. v dd rr rr 100r 0.01c adc v dd 0.2r 0.2r 1k ? u 1 mcp6v91 + - + - r f 10 nf adc v dd r n 1.0 f v dd r w r t r b r rtd r g 100 ? 1.00 k ? 4.99 k ? 34.8 k ? 2.00 m ? 10.0 k ? u 1 mcp6v91 r w 10.0 k ? r f 2.00 m ? 10 nf 100 nf + - + -
mcp6v91/1u/2/4 ds20005434b-page 24 ? 2015-2016 microchip technology inc. 4.4.3 offset voltage correction figure 4-13 shows mcp6v91 (u 2 ) correcting the input offset voltage of another op amp (u 1 ). r 2 and c 2 integrate the offset error seen at u 1 ?s input. the integration needs to be slow enough to be stable (with the feedback provided by r 1 and r 3 ). r 4 and r 5 attenuate the integrator?s output. this shifts the integrator pole down in frequency. figure 4-13: offset correction. 4.4.4 precision comparator use high gain before a comparator to improve the latter?s performance. do not use mcp6v91/1u/2/4 as a comparator by itself; the v os correction circuitry does not operate properly without a feedback loop. figure 4-14: precision comparator. u 1 mcp6xxx c 2 r 2 r 1 r 3 v dd /2 r 4 v in v out r 2 v dd /2 r 5 u 2 mcp6v91 + - + - v in r 3 r 2 v dd /2 v out r 5 r 4 r 1 u 1 mcp6v91 u 2 mcp6541 + - + -
? 2015-2016 microchip technology inc. ds20005434b-page 25 mcp6v91/1u/2/4 notes:
mcp6v91/1u/2/4 ds20005434b-page 26 ? 2015-2016 microchip technology inc. 5.0 design aids microchip provides the basic design aids needed for the mcp6v91/1u/2/4 family of op amps. 5.1 filterlab ? software microchip?s filterlab ? software is an innovative software tool that simplifies analog active filter (using op amps) design. available at no cost from the microchip web site at www.microchip.com/filterlab , the filterlab design tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance. 5.2 microchip advanced part selector (maps) maps is a software tool that helps efficiently identify microchip devices that fit a particular design requirement. available at no cost from the microchip web site at www.microchip.com/maps , maps is an overall selection tool for microchip?s product portfolio that includes analog, memory, mcus and dscs. using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase and sampling of microchip parts. 5.3 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demonstration and evaluation boards that are designed to help customers achieve faster time to market. for a complete listing of these boards and their corresponding user?s guides and technical information, visit the microchip web site at www.microchip.com/analog tools . some boards that are especially useful are: ? mcp6v01 thermocouple auto-zeroed reference design (mcp6v01rd-tcpl) ? mcp6xxx amplifier evaluation board 1 (ds51667) ? mcp6xxx amplifier evaluation board 2 (ds51668) ? mcp6xxx amplifier evaluation board 3 (ds51673) ? mcp6xxx amplifier evaluation board 4 (ds51681) ? active filter demo board kit user?s guide (ds51614) ? 8-pin soic/msop/tsso p/dip evaluation board (soic8ev) ? 14-pin soic/tssop/dip evaluation board (soic14ev) 5.4 application notes the following microchip application notes are available on the microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. adn003: ?select the right operational amplifier for your filtering circuits? (ds21821) an722: ?operational amplifier topologies and dc specifications? (ds00722) an723: ?operational amplifier ac specifications and applications? (ds00723) an884: ?driving capacitive loads with op amps? (ds00884) an990: ?analog sensor conditioning circuits ? an overview? (ds00990) an1177: ?op amp precision design: dc errors? (ds01177) an1228: ?op amp precision design: random noise ? (ds01228) an1258: ?op amp precision design: pcb layout techniques? (ds01258) an1767: ?solutions for radio frequency electromagnetic interference in amplifier circuits? (ds00001767) these application notes and others are listed in the design guide: ?signal chain design guide? (ds21825)
? 2015-2016 microchip technology inc. ds20005434b-page 27 mcp6v91/1u/2/4 notes:
mcp6v91/1u/2/4 ds20005434b-page 28 ? 2015-2016 microchip technology inc. 6.0 packaging information 6.1 package marking information 5-lead sc70 ( mcp6v91u ) example 5-lead sot-23 (mcp6v91, mcp6v91u) example device code mcp6v91t-e/ot aabjy mcp6v91ut-e/ot aabky dw56 device code mcp6v91ut-e/lty dwnn xxxxy wwnnn aabj5 10256 8-lead msop ( mcp6v92 ) example 6v92 544256 8-lead tdfn (mcp6v92) example acy 544 25 device code mcp6v92t-e/mny acy note: applies to 8-lead 2x3 tdfn.
? 2015-2016 microchip technology inc. ds20005434b-page 29 mcp6v91/1u/2/4 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 14-lead tssop ( mcp6v94 )example yyww nnn xxxxxxxx mcp6v94 1544 256
mcp6v91/1u/2/4 ds20005434b-page 30 ? 2015-2016 microchip technology inc. 5-lead plastic small outine transistor (lty) [sc70] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technology drawing c04-083b d b 1 2 3 e1 e 4 5 ee c l a1 aa2
? 2015-2016 microchip technology inc. ds20005434b-page 31 mcp6v91/1u/2/4 5-lead plastic small outine transistor (lty) [sc70] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6v91/1u/2/4 ds20005434b-page 32 ? 2015-2016 microchip technology inc. n b e e1 d 1 2 3 e e1 a a1 a2 c l l1
? 2015-2016 microchip technology inc. ds20005434b-page 33 mcp6v91/1u/2/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6v91/1u/2/4 ds20005434b-page 34 ? 2015-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2015-2016 microchip technology inc. ds20005434b-page 35 mcp6v91/1u/2/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6v91/1u/2/4 ds20005434b-page 36 ? 2015-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2015-2016 microchip technology inc. ds20005434b-page 37 mcp6v91/1u/2/4 b a 0.15 c 0.15 c 0.10 c a b 0.05 c (datum b) (datum a) c seating plane note 1 12 n 2x top view side view bottom view note 1 12 n 0.10 c a b 0.10 c a b 0.10 c 0.08 c microchip technology drawing no. c04-129-mny rev d sheet of 2 2x 8x for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 8-lead plastic dual flat, no lead package (mny) C 2x3x0.75mm body [tdfn] d e d2 e2 a (a3) a1 e 8x b l k
mcp6v91/1u/2/4 ds20005434b-page 38 ? 2015-2016 microchip technology inc. microchip technology drawing no. c04-129-mny rev d sheet 2 of 2 8-lead plastic dual flat, no lead package (mny) C 2x3x0.75mm body [tdfn] for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: nom millimeters 0.50 bsc 2.00 bsc 3.00 bsc 0.20 ref 1. pin 1 visual index feature may vary, but must be located within the hatched area. bsc: basic dimension. theoretically exact value shown withou t tolerances. ref: reference dimension, usually without tolerance, for information purposes only. contact-to-exposed pad contact thickness exposed pad width exposed pad length 4. dimensioning and tolerancing per asme y14.5m 3. package is saw singulated 2. package may have one or more exposed tie bars at ends. notes: contact width overall width overall length contact length standoff number of pins overall height pitch k 0.20 units n e a dimension limits d a3 a1 b d2 e2 e l 0.20 1.45 1.60 0.25 0.00 0.70 min - - 0.25 0.30 - - 1.80 0.30 0.45 1.65 8 0.75 0.02 0.05 0.80 max
? 2015-2016 microchip technology inc. ds20005434b-page 39 mcp6v91/1u/2/4 recommended land pattern dimension limits units optional center pad width optional center pad length contact pitch y2 x2 1.80 1.65 millimeters 0.50 bsc min e max contact pad length (x8) contact pad width (x8) y1 x1 0.85 0.25 microchip technology drawing no. c04-129-mny rev. a nom 8-lead plastic dual flat, no lead package (mny) C 2x3x0.75mm body [tdfn] 12 8 c contact pad spacing 2.90 thermal via diameter v thermal via pitch ev 0.30 1.00 bsc: basic dimension. theoretically exact value shown without tolerances. notes: dimensioning and tolerancing per asme y14.5m for best soldering results, thermal vias, i f used, should be filled or tented to avoid solder loss during reflow process 1. 2. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: c e x1 y1 y2 x2 ev ev ?v silk screen
mcp6v91/1u/2/4 ds20005434b-page 40 ? 2015-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2015-2016 microchip technology inc. ds20005434b-page 41 mcp6v91/1u/2/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6v91/1u/2/4 ds20005434b-page 42 ? 2015-2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2015-2016 microchip technology inc. ds20005434b-page 43 mcp6v91/1u/2/4 appendix a: revision history revision b (march 2016) the following is the list of modifications: 1. added new devices to the family: mcp6v92 and mcp6v94, and related information throughout the document. 2. added figure 2-37 . 3. updated ta b l e 3 - 1 in section 3.0, pin descrip- tions . 4. added markings and specification drawings for the new packages in section 6.0, packaging information . 5. updated the product identification system section with the new packages. 6. corrected typographical errors. revision a (september 2015) ? original release of this document.
mcp6v91/1u/2/4 ds20005434b-page 44 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds20005434b-page 45 mcp6v91/1u/2/4 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp6v91t: single op amp (tape and reel) (sot-23 only) mcp6v91ut: single op amp (tape and reel) (sc-70, sot-23) mcp6v92: dual op amp (msop, 2x3 tdfn) mcp6v92t: dual op amp (tape and reel) (msop, 2x3 tdfn) mcp6v94: quad op amp (tssop) mcp6v94t: quad op amp (tape and reel) (tssop) temperature range: e = -40c to +125c (extended) package: lty* = plastic small outline transistor, sc-70, 5-lead ot = plastic small outline transistor, sot-23, 5-lead mny* = plastic dual flat, no-lead - 230.75 mm body, tdfn, 8-lead ms = plastic micro small outline, msop, 8-lead st = plastic thin shrink small outline - 4.4 mm body, tssop, 14-lead *y = nickel palladium gold manufacturing designator. only available on the sc70 and tdfn packages. part no. ?x /xx package temperature range device [x] (1) tape and reel examples: a) mcp6v91t-e/ot: tape and reel, extended temperature, 5ld sot-23 package a) mcp6v91ut-e/lty: tape and reel extended temperature, 5ld sc70 package b) mcp6v91ut-e/ot: tape and reel, extended temperature, 5ld sot-23 package a) mcp6v92-e/ms: extended temperature, 8ld msop package b) mcp6v92t-e/ms: tape and reel, extended temperature, 8ld msop package c) mcp6v92t-e/mny: tape and reel, extended temperature, 8ld 2x3 tdfn package a) mcp6v94-e/st: extended temperature, 14ld tssop package b) mcp6v94t-e/st: tape and reel, extended temperature, 14ld tssop package note 1: tape and reel identifier only appears in the catalog part number description. this identi- fier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option.
mcp6v91/1u/2/4 ds20005434b-page 46 ? 2015-2016 microchip technology inc. notes:
? 2015-2016 microchip technology inc. ds20005434b-page 47 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015-2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0312-8 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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